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Freescale Semiconductor Data Sheet
Document Number: SCF5249EC Rev. 0, 04/2005
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet
1
Introduction
Table of Contents
1 2 3 4 5 6 7 8 9 10 Introduction..........................................................1 SCF5249 Block Diagram .....................................3 SCF5249 Feature Details ....................................3 160 MAPBGA Ball Assignments .........................6 SCF5249 Functional Overview............................7 General Device Information...............................12 Documentation ..................................................12 Signal Descriptions............................................13 Electrical Characteristics ...................................28 Pin-Out and Package Information .....................46
This document provides an overview of the SCF5249 ColdFire(R) processor and general descriptions of SCF5249 features and its various modules. The SCF5249 was designed as a system controller/decoder for MP3 music players, especially portable MP3 CD players. The 32-bit ColdFire core with Enhanced Multiply Accumulate (EMAC) unit provides optimum performance and code density for the combination of control code and signal processing required for MP3 decode, file management, and system control. Low power features include a hardwired CD ROM decoder, advanced 0.18um CMOS process technology, 1.8V core power supply, and on-chip 96KByte SRAM. MP3 decode requires less than 20MHz CPU bandwidth and runs in on-chip SRAM with external access only for data input and output. The SCF5249 is also an excellent general purpose system controller with over 125 Dhrystone 2.1 MIPS @ 140MHz performance at a very competitive price. The
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
Introduction
integrated peripherals and EMAC allow the SCF5249 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins.
1.1
1.1.1
Orderable Parts Numbers
Orderable Part Table
Table 1. Orderable Part Numbers
Orderable Part Number Maximum Clock Frequency 120 MHz 120 MHz 140 MHz 140 MHz Package Type 144 pin QFP 144 pin QFP 160 ball MAPBGA 160 ball MAPBGA Operating Temperature Range -20C to 70C -20C to 70C -20C to 70C -20C to 70C Part Status Leaded Lead Free Leaded Lead Free
SCF5249LPV120 SCF5249LAG120 SCF5249VF140 SCF5249VM140
1.2
SCF5249 Features
The SCF5249 integrated microprocessor combines a Version 2 ColdFire(R) processor core operating at 140MHz with the following modules. * DMA controller with 4 DMA channels * Integrated Enhanced Multiply-accumulate Unit (EMAC) * 8-KByte Direct Mapped Instruction Cache * 96-KByte SRAM (A 64K and a 32K bank) * Operates from external crystal oscillator * Supports 16-bit wide SDRAM memories * Serial Audio Interface which supports IIS and EIAJ audio protocols * Digital audio transmitter and two receivers compliant with IEC958 audio protocol * CD-ROM and CD-ROM XA block decoding and encoding function * Two UARTS * Queued Serial Peripheral Interface (QSPI) (Master Only) * Two timers * IDE and SmartMedia interfaces * Analog/Digital Converter * Flash Memory Card Interface * Two I2C modules * * System debug support General Purpose I/O pins shared with other functions
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 2 Freescale Semiconductor
SCF5249 Block Diagram
* * *
1.8V core, 3.3V I/O 160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at 120 MHz) -200 C to 700 C ambient operating temperature range
2
SCF5249 Block Diagram
CD ROM Block Decoder Encoder CD Text Interface QSPI 12-bit ADC
DUART
8K byte I-Cache
ColdFire V2
I Addr Gen I Fetch
B u s C o n t r o l
Serial Audio Interface 3 x I2S Rx 2 x I2S Tx
96K Byte SRAM
Instr Buf Dec&Sel Op A Gen & Ex
SPDIF/EBU Transmitter
IDE Interface Flash Media Interface
EMAC
Debug Module
M-bus (I2C)
Timers
SDRAM Cntr & Chip Selects
General Purpose I/O
SPDIF/EBU Receiver
DMA
PLL Frequency Synthesizer
Figure 1. SCF5249 Block Diagram
3
SCF5249 Feature Details
The primary features of the SCF5249 integrated processor include the following: * ColdFire V2 Processor Core operating at 140MHz -- Clock-doubled Version 2 microprocessor core -- 32-bit internal data bus, 16 bit external data bus -- 16 user-visible, 32-bit general-purpose registers -- Supervisor/user modes for system protection -- Vector base register to relocate exception-vector table -- Optimized for high-level language constructs
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 3
SCF5249 Feature Details
*
DMA controller -- Four fully programmable channels: Two dedicated to the audio interface module and two dedicated to the UART module (External requests are not supported.) -- Supports dual- and single-address transfers with 32-bit data capability -- Two address pointers that can increment or remain constant -- -- -- -- -- -- -- 16-/24-bit transfer counter Operand packing and unpacking support Auto-alignment transfers supported for efficient block movement Supports bursting and cycle stealing All channels support memory to memory transfers Interrupt capability Provides two clock cycle internal access
*
*
*
*
*
Enhanced Multiply-accumulator Unit -- Single-cycle multiply-accumulate operations for 32 x 32 bit and 16 x 16 bit operands -- Support for signed, unsigned, integer, and fixed-point fractional input operands -- Four 48-bit accumulators to allow the use of a 40-bit product -- The addition of 8 extension bits to increase the dynamic number range -- Fast signed and unsigned integer multiplies 8-KByte Direct Mapped instruction cache -- Clock-doubled to match microprocessor core speed -- Flush capability -- Non-blocking cache provides fast access to critical code and data 96-KByte SRAM -- Provides one-cycle access to critical code and data -- Split into two banks, SRAM0 (32K), and SRAM1 (64K) -- DMA requests to/from internal SRAM1 supported Crystal Trim -- The XTRIM output can be used to trim an external crystal oscillator circuit which would allow lock with an incoming IEC958 or serial audio signal Audio Interfaces -- IEC958 input and output -- Four serial Philips IIS/Sony EIAJ interfaces - One with input and output, one with output only, two with input only (Three inputs, two outputs) - Master and Slave operation
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 4 Freescale Semiconductor
SCF5249 Feature Details
* *
*
*
* *
*
*
CD Text Interface -- Allows the interface of CD subcode (transmitter only) Dual Universal Synchronous/asynchronous Receiver/Transmitter (Dual UART) -- Full duplex operation -- Baud-rate generator -- Modem control signals: clear-to-send (CTS) and request-to-send (RTS) -- DMA interrupt capability -- Processor-interrupt capability Queued Serial Peripheral Interface (QSPI) -- Programmable queue to support up to 16 transfers without user intervention -- Supports transfer sizes of 8 to 16 bits in 1-bit increments -- Four peripheral chip-select lines for control of up to 15 devices -- Baud rates from 273 Kbps to 17.5 Mbps at 140MHz -- Programmable delays before and after transfers -- Programmable clock phase and polarity -- Supports wraparound mode for continuous transfers -- Master mode only Dual 16-bit General-purpose Multimode Timers -- Clock source selectable from external, CPU clock/2 and CPU clock/32. -- 8-bit programmable prescaler -- 2 timer inputs and 2 outputs -- Processor-interrupt capability -- 14.3 nS resolution with CPU clock at 140MHz IDE/ SmartMedia Interface -- Allows direct connection to an IDE hard drive or other IDE peripheral Analog/Digital Converter -- 12-Bit Resolution -- 4 Muxed inputs Flash Memory Card Interface -- Allows connection to Sony MemoryStick compatible devices -- Support SD cards and other types of flash media Dual I2C Interfaces -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads -- Master and slave modes, support for multiple masters -- Automatic interrupt generation with programmable level
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 5
160 MAPBGA Ball Assignments
*
*
* * *
System debug support -- Real-time instruction trace for determining dynamic execution path -- Background debug mode (BDM) for debug features while halted -- Debug exception processing capability -- Real-time debug support System Interface -- Glueless bus interface with four chip selects and DRAMC support for interface to 16-bit for DRAM, SRAM, ROM, FLASH, and I/O devices - Two programmable chip-select signals for static memories or peripherals, with programmable wait states and port sizes. - Two dedicated chip selects for 16-bit wide DRAM /SDRAM. - CS0 is active after reset to provide boot-up from external FLASH/ROM. -- Programmable interrupt controller - Low interrupt latency - Eight external interrupt requests - Programmable autovector generator -- 44 programmable general-purpose inputs* -- 46 programmable general-purpose outputs* - * For the 160 MAPBGA package -- IEEE 1149.1 Test (JTAG) Module Clocking -- Clock-multiplied PLL, programmable frequency 1.8V Core, 3.3V I/O 160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at 120 MHz)
4
160 MAPBGA Ball Assignments
NOTE The 144 QFP part is qualified for 120 MHz operation. The 160MAPBGA part is qualified for 140 MHz.
The following signals are not available on the 144 QFP package.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 6 Freescale Semiconductor
SCF5249 Functional Overview
Table 2. 160 MAPBGA Ball Assignments
160 MAPBGA Ball Number E3 G4 H3 K3 L4 L8 N8 P9 K11 G12 F13 F12 E8 B8 E7 A7 Function cmd_sdio2 sdata0_sdio1 RSTO/sdata2_bs2 A25 QSPI_CS1 QSPI_CS3 SDRAM_CS2 EbuOut2 BUFENb2 subr sfsy rck SRE lrck3 SWE sclk3 gpo8 gpio24 gpio22 gpio7 gpo 37 gpio17 gpio 53 gpio 52 gpio 51 gpio11 gpio 45 gpio12 gpio 49 GPIO gpio34 gpio54
5
5.1
SCF5249 Functional Overview
ColdFire V2 Core
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit (ALU).
5.2
DMA Controller
The SCF5249 provides four fully programmable DMA channels for quick data transfer. Single and dual address mode is supported with the ability to program bursting and cycle stealing. Data transfer is selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 7
SCF5249 Functional Overview
Two internal audio channels and the dual UART can be used with the DMA channels. All channels can perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and a programmable DMA exception handler. External requests are not supported.
5.3
Enhanced Multiply and Accumulate Module (EMAC)
The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture. The EMAC provides functionality in three related areas: 1. Faster signed and unsigned integer multiplies 2. New multiply-accumulate operations supporting signed and unsigned operands 3. New miscellaneous register operations Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution pipeline.
5.4
Instruction Cache
The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock. The SCF5249 processor uses a 8K-byte, direct-mapped instruction cache to achieve 125 MIPS at 140 Mhz. The cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port sizes to quickly fill cache lines.
5.5
Internal 96-KByte SRAM
The 96-KByte on-chip SRAM is split over two banks, SRAM0 (32k) and SRAM1 (64K). It provides one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data segments to maximize performance. Memory in the second bank can be accessed under DMA.
5.6
DRAM Controller
The SCF5249 DRAM controller provides a glueless interface for up to two banks of DRAM, each of which can be up to 32 MBytes. The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMS.
5.7
System Interface
The SCF5249 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with independent programmable control of the assertion and negation of chip-select and write-enable signals. The SCF5249 also supports bursting ROMs.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 8 Freescale Semiconductor
SCF5249 Functional Overview
5.8
External Bus Interface
The bus interface controller transfers information between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. The external bus interface provides 23 bits of address bus space, a 16-bit data bus, Output Enable, and Read/Write signals. This interface implements an extended synchronous protocol that supports bursting operations.
5.9
Serial Audio Interfaces
The SCF5249 digital audio interface provides four serial Philips IIS/Sony EIAJ interfaces. One interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other three interfaces are 3-pin (1 bit clock, 1 word clock, 1 data in or out). The serial interfaces have no limit on minimum sampling frequency. Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the frequency of the internal system clock.
5.10 IEC958 Digital Audio Interfaces
The SCF5249 has two digital audio input interfaces, and one digital audio output interface. There are four digital audio input pins, two digital audio output pins. An internal multiplexer selects one of the four inputs to the digital audio input interface. There is one digital audio output interface but it has two IEC958 outputs. One output carries the professional "c" channel, and the other carries the consumer "c" channel. The rest carry identical data. The IEC958 output can take the output from the internal IEC958 generator, or multiplex out one of the four IEC958 inputs.
5.11 Audio Bus
The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. Each transmitter has a source select register. In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three of these registers allow data reads from the audio bus and allow selection of the audio source. The other three register provide a write path to the audio bus and can be selected by transmitters as the audio source. Through these registers, the CPU has access to the audio samples for processing. Audio can be routed from a receiver to a transmitter without the data being processed by the core so the audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format conversion.
5.12 CD-ROM Encoder/Decoder
The SCF5249 is capable of processing CD-ROM sectors in hardware. Processing is compliant with CD-ROM and CD-ROM XA standards.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 9
SCF5249 Functional Overview
The CD-ROM decoder performs following functions in hardware: * Sector sync recognition * Descrambling of sectors * Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors * Third-layer error correction is not performed The CD-ROM encoder performs following functions in hardware: * Sector sync recognition * Scrambling of sectors * Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors. * Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of performance for single-speed.
5.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also provides several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines. The system clock provides the clocking function from a programmable prescaler. You can select full duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs can interrupt the CPU on various normal or error-condition events.
5.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to 16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to 37 Mbits/second are possible at a CPU clock of 140 MHz. The QSPI supports master mode operation only.
5.15 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes: 1. Timer Capture. This mode captures the timer value with an external event. 2. Output Capture. This mode triggers an external signal or interrupts the CPU when the timer reaches a set value 3. Event Counter. This mode counts external events. The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. In addition to the /1 and /16 clock derived from the bus clock (CPU clock / 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 10 Freescale Semiconductor
SCF5249 Functional Overview
5.16 IDE and SmartMedia Interfaces
The SCF5249 system bus allows connection of an IDE hard disk drive and SmartMedia flash card with a minimum of external hardware. The external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE bus. The control signals for the buffers are generated in the SCF5249.
5.17 Analog/Digital Converter (ADC)
The four channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. The digital portion of the ADC is provided internally. The analog voltage comparator must be provided externally as well as an external integrator circuit (resistor/capacitor) which is driven by the ADC output. A software interrupt is provided when the ADC measurement cycle is complete.
5.18 Flash Memory Card Interface
The interface is Sony MemoryStick and SecureDigital compatible. However, there is no hardware support for MagicGate.
5.19 I2C Module
The two-wire I2C bus interface, which is compliant with the Philips I2C bus standard, is a bidirectional serial bus that exchanges data between devices. The I2C bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. Bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected.
5.20 Chip-Selects
Two programmable chip-select outputs provide signals that enable glueless connection to external memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion are programmable with configuration registers. These signals also interface to 16-bit ports. CS0 is active after reset to provide boot-up from external FLASH/ROM.
5.21 GPIO Interface
A total of 44 General Purpose inputs and 46 General Purpose outputs are available. These are multiplexed with various other signals. Eight of the GPIO inputs have edge sensitive interrupt capability.
5.22 Interrupt Controller
The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49 internal interrupt sources. In addition, there are 8 GPIOs where interrupts can be generated on the rising or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 11
General Device Information
5.23 JTAG
To help with system diagnostics and manufacturing testing, the SCF5249 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A standard. Freescale provides BSDL files for JTAG testing.
5.24 System Debug Interface
The ColdFire processor core debug interface supports real-time instruction trace and debug, plus background-debug mode. A background-debug mode (BDM) interface provides system debug. In real-time instruction trace, four status lines provide information on processor activity in real time (PST pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses, which helps track the machine's dynamic execution path.
5.25 Crystal and On-chip PLL
Typically, an external 16.92 Mhz or 33.86 Mhz clock input is used for CD R/W applications, while an 11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip programmable PLL, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 Mhz). Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is only available when the 33.86 Mhz crystal is connected. The SCF5249 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100 ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.
6 7
General Device Information Documentation
The SCF5249 is available in a 160-pin MAP BGA package, or a 144-pin QFP package.
Table 3 lists the documents that provide a complete description of the SCF5249 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the internet; http://www.freescale.com/ (the source for the latest information).
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 12 Freescale Semiconductor
Signal Descriptions
Table 3. SCF5249 Documentation
Document Name CFPRM/D ColdFire2UM ColdFire2UMAD SCF5249UM Description ColdFire Family Programmer's Reference Manual Version 2/2M ColdFire Core Processor User's Manual Version 2/2M ColdFire Core Processor User's Manual Addendum SCF5249 User's Manual Order Number CFPRM/D ColdFire2UM/D ColdFire2UMAD/D SCF5249UM/D
8
8.1
Signal Descriptions
Introduction
Table 4. SCF5249 Signal Index
Signal Name Mnemonic A[23:1] A[25]/GPO8 RW_b OE D[31:16] Function 23 address lines, address line 25 multiplexed with gpo8. Bus write enable - indicates if read or write cycle in progress Output enable for asynchronous memories connected to chip selects Data bus used to transfer word data Row address strobe for external SDRAM. Column address strobe for external SDRAM Write enable for external SDRAM Indicates during write cycle if high byte is written Indicates during write cycle if low byte is written SDRAM chip select SDRAM chip select SDRAM clock enable SDRAM clock output Input/ Output Out Out Out In/Out Out Out Out Out Out Outt In/Out Out In/Out negated negated Reset State X H negated Hi-Z negated negated negated
This section describes the SCF5249 input and output signals. The signal descriptions as shown in Table 4 are grouped according to relevant functionality.
Address Read-write control Output enable Data
Synchronous row address SDRAS strobe Synchronous column address strobe SDRAM write enable SDRAM upper byte enable SDCAS SDWE SDUDQM
SDRAM lower byte enable SDLDQM SDRAM chip selects SDRAM chip selects SDRAM clock enable System clock SDRAMCS1 SDRAMCS2/GPIO7 BCLKE SCLK/GPIO10
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 13
Signal Descriptions
Table 4. SCF5249 Signal Index (continued)
Signal Name ISA bus read strobes ISA bus write strobes Mnemonic CS2/IDE-DIOR/GPIO13 CS3/SRE/GPIO11 IDE-DIOW/GPIO14 SWE/GPIO12 IDE-IORDY/GPIO16 CS0 CS1/GPIO58 Function There are 2 ISA bus read strobes and 2 ISA bus write strobes. They allow connection of two independent ISA bus peripherals, e.g. an IDE slave device and a SmartMedia card. ISA bus wait line - available for both busses Enables peripherals at programmed addresses. CS[1:0]. CS[0]provides boot ROM selection Two programmable buffer enables allow seamless steering of external buffers to split data and address bus in sections. Transfer Acknowledge signal Clock signal for first I C module operation Signal is also QSPI clock Serial data port first I2C module operation Signal is also QSPI data in Clock signal for second I2C module operation Serial data port for second I2C module operation Signal is receive serial data input for DUART Signal is transmit serial data output for DUART DUART signals a ready to receive data query Signals to DUART that data can be transmitted to peripheral CTS2 is multiplexed with an A/D input Provides clock input to timer or provides trigger to timer value capture logic Capable of output waveform or pulse generation
2
Input/ Output In/Out In/Out
Reset State
ISA bus wait signal Chip Selects[1:0]
In/Out Out In/Out negated
Buffer enable 1 Buffer enable 2
BUFENB1/GPIO57 BUFENB2/GPIO7
In/Out In/Out
Transfer acknowledge Serial Clock Line
TA/GPIO20 SCL0/QSPI_CLK
In/Out In/Out
Serial Data Line
SDA0/QSPI_DIN
In/Out
Serial Clock Line Serial Data Line Receive Data Transmit Data Request-To-Send Clear-To-Send
SCL1_GPIO_3 SDA1_GPIO55 RXD1/GPI28/ADIN2 RXD0/GPI27 TXD1/GPO28 TXD0/GPO27 RTS1/GPO31 RTS2/GPO30 CTS1/ADIN3/GPI31 CTS0/GPI30
In/Out In/Out In Out Out In asserted negated
Timer Input
TIN0/GPI33 TIN1/GPIO23 TOUT0/GPO33 TOUT1/ADOUT/GPO35
In In/Out Out
Timer Output
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 14 Freescale Semiconductor
Signal Descriptions
Table 4. SCF5249 Signal Index (continued)
Signal Name IEC958 inputs Mnemonic EBUIN1/GPI36 EBUIN2/GPI37 EBUIN3/ADIN0/GPI38 EBUIN4/ADIN1/GPI39 EBUOUT1/GPO36 EBUOUT2/GPO37 SDATAI1 SDATAI3/GPI41 SDATA14/GPI42 SDATAO1/GPIO25 SDATAO2/GPO41 LRCK1 LRCK2/GPIO44 LRCK3/GPIO45 LRCK4/GPIO46 SCLK1 SCLK2/GPIO48 SCLK3/GPIO49 SCLK4/GPIO50 EF/GPIO19 CFLG/GPIO18 RCK/GPIO51 SFSY/GPIO52 SUBR/GPIO53 XTRIM/GPO38 MCLK1/GPIO39 MCLK2/GPIO42 Function Audio interfaces IEC958 inputs multiplexed with some A/D inputs Input/ Output In Reset State
IEC958 outputs Serial data in
Audio interfaces IEC958 outputs Audio interfaces serial data inputs
Out In
Serial data out Word clock
Audio interfaces serial data outputs Audio interfaces serial word clocks
In/Out Out In/Out
Bit clock
Audio interfaces serial bit clocks
In/Out
Serial input Serial input Subcode clock Subcode sync Subcode data Clock frequency trim Audio clocks out
Error flag serial in C-flag serial in Audio interfaces subcode clock Aaudio interfaces subcode sync Audio interfaces subcode data Clock trim control DAC output clocks Secure Digital command lane MemoryStick interface 2 data i/o Clock out for both MemoryStick interfaces and for Secure Digital SecureDigital serial data bit 0 MemoryStick interface 1 data i/o SecureDigital serial data bit 1 MemoryStick interface 1 strobe SecureDigital serial data bit 2 MemoryStick interface 2 strobe Reset output signal SecureDigital serial data bit 3
In/Out In/Out In/Out In/Out In/Out Out Out In/Out In/Out In/Out In/Out In/Out
MemoryStick/SecureDigit CMDSDIO2/GPIO34 al interface SCLKOUT/GPIO15 SDATA0_SDIO1/GPIO54 SDATA1_BS1/GPIO9 RSTO/SDATA2_BS2
SDATA3/GPIO56
In/Out
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 15
Signal Descriptions
Table 4. SCF5249 Signal Index (continued)
Signal Name ADC Mnemonic EBUIN3/ADIN0/GPI38 EBUIN4/ADIN1/GPI39 RXD2/ADIN2/GPI28 CTS2/ADIN3/GPI31 TOUT1/ADOUT/GPO35 SCL/QSPI_CLK SDA/QSPI_DIN QSPIDOUT/GPIO26 QSPICS0/GPIO29 QSPICS1/GPIO24 QSPICS2/GPIO21 QSPICS3/GPIO22 CRIN RSTI TEST[3:0] HIZ DDATA3/GPIO4 DDATA2/GPIO2 DDATA1/GPIO1 DDATA0/GPIO0 PST3/GPIO62 PST2/GPIO61 PST1/GPIO60 PST0/GPIO59 PSTCLK/GPO63 TCK TRST/DSCLK Function Analog to Digital converter input signals Input/ Output In/Out Reset State
ADC QSPI clock QSPI data in QSPI data out QSPI chip selects
Analog to digital convertor output signal. QSPI clock signal QSPI data input QSPI data out QSPI chip selects
In/Out In/Out In/Out In/Out In/Out
Crystal in Reset In Freescale Test Mode High Impedance Debug Data
Crystal input Processor Reset Input Should always be low. Assertion three-states all output signal pins. Displays captured processor data and break-point status.
In In In In In/Out Hi-Z
Processor Status
Indicates internal processor status.
In/Out
Hi-Z
Processor clock Test Clock Test Reset/Development Serial Clock
Processor clock output Clock signal for IEEE 1149.1A JTAG. Multiplexed signal that is asynchronous reset for JTAG controller. Clock input for debug module. Multiplexed signal that is test mode select in JTAG mode and a hardware break-point in debug mode. Multiplexed serial input for the JTAG or background debug module. Multiplexed serial output for the JTAG or background debug module.
Out In In
Test Mode Select/ Break Point
TMS/BKPT
In
Test Data Input / TDI/DSI Development Serial Input Test Data Output/Development Serial Output TDO/DSO
In Out
Note: The CMD_SDIO2, SDATA0_SDIO1, RSTO/SDATA2_BS2, A25, QSPI_CS1, QSPI_CS3, SDRAM_CS2, EBUOUT2, BUFENB2, SUBR, SFSY, RCK, SRE, LRCK3, SWE, and the SCLK3 signals are only used in the 160 MAPBGA package.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 16 Freescale Semiconductor
Signal Descriptions
8.2
GPIO
Many pins have a GPIO as first or second function. If GPIO is second function, following rules apply: * General purpose input is always active, regardless of state of pin. * General purpose output or primary output is determined by value written to GPIO function select register. * Power-on reset function is not GPIO.
8.3
8.3.1
*
SCF5249 Bus Signals
Address Bus
The address bus provides the address of the byte or most significant byte of the word or longword being transferred.The address lines also serve as the DRAM address pins, providing multiplexed row and column address signals. Bits 23 down to 1 and 25 of the address are available. A25 is intended to be used with 256 Mbit DRAM's. Signals are named: A[23:1] A[25]/GPO8
These signals provide the external bus interface to the SCF5249.
* * *
8.3.2
Read-Write Control
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and a high is a read cycle.
8.3.3
Output Enable
The OE signal is intended to be connected to the output enable of asynchronous memories connected to chip selects. During bus read cycles, the ColdFire processor will drive OE low.
8.3.4
Data Bus
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5249 on the rising clock edge. The port width for each chip-select and DRAM bank are programmable. The data bus uses a default configuration if none of the chip-selects or DRAM bank match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or operand size.
8.3.5
Transfer Acknowledge
The TA/GPIO20 pin is the transfer acknowledge signal.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 17
Signal Descriptions
8.4
SDRAM Controller Signals
Table 5. SDRAM Controller Signals
SDRAM Signal Synchronous DRAM row address strobe Synchronous DRAM Column Address Strobe Synchronous DRAM Write Synchronous DRAM Chip Enable Description The SDRAS active low pin provides a seamless interface to the RAS input on synchronous DRAM The SDCAS active low pin provides a seamless interface to CAS input on synchronous DRAM. The SDWE active-low pin is asserted to signify that a SDRAM write cycle is underway. This pin outputs logic `1' during read bus cycles. The SD_CS1 and The SDRAM_CS2/GPIO7 active-low output signal is used during synchronous mode to route directly to the chip select of up to two SDRAM devices. The SDRAM_CS2/gpio7 can be programmed to be gpio using the GPIO-FUNCTION register. The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM and SDLDQM byte enable outputs. The DRAM clock is driven by the SCLK signal The BCLKE active high output signal is used during synchronous mode to route directly to the SCKE signal of external SDRAMs. This signal provides the clock enable to the SDRAM.
The following SDRAM signals provide a seamless interface to external SDRAM. An SDRAM width of 16 bits is supported and can access as much as 64 Mybtes of memory. ADRAMs are not supported.
Synchronous DRAM UDQM and LQDM signals Synchronous DRAM clock Synchronous DRAM Clock Enable
NOTE The SDRAM_CS2 signal is only used on the 160 MAPBGA package.
8.5
Chip Selects
There are two chip select outputs on the SCF5249 device. CS0 and CS1/GPIO58. The second signal is multiplexed with a GPIO signal. The active low chip selects can be used to access asynchronous memories. The interface is glueless.
8.6
ISA Bus
The SCF5249 supports an ISA bus. (No ISA DMA channel). Using the ISA bus protocol, reads and writes to up to two ISA bus peripherals are possible. For the first peripheral, CS2/IDE-DIOR/GPIO13 and IDE-DIOW/GPIO14 are the read and write strobe. For the second peripheral, CS3/SRE/GPIO11 and SWE/GPIO12 are the read and write strobe. Either peripheral can insert wait states by pulling IDE-IORDY/GPIO16
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 18 Freescale Semiconductor
Signal Descriptions
8.7
Bus Buffer Signals
As the SCF5249 has a quite complicated slave bus, with the possibility to put DRAM on the bus, put asynchronous memories on the bus, and to put ISA bus peripherals on the bus, it may become necessary to introduce a bus buffer on the bus. The SCF5249 has a glueless interface to steer these bus buffers with 2 bus buffer output signals BUFENB1/GPIO57 and BUFENB2/GPIO7. NOTE The BUFENB2 signal is only used in the 160 MAPBGA package.
8.8
I2C Module Signals
There are two I2C interfaces on this device. The I2C module acts as a quick two-wire, bidirectional serial interface between the SCF5249 processor and peripherals with an I2C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When devices connected to the I2C bus drive the bus, they will either drive logic-0 or high-impedance. This can be accomplished with an open-drain output.
Table 6. I2C Module Signals
I2c Module Signal I2C Serial Clock Description The SCL/QPSICLK and SCL2/GPIO3 bidirectional signals are
the clock signal for first and second I2C module operation. The I2C module controls this signal when the bus is in master mode; all I2C devices drive this signal to synchronize I2C
timing. Signals are multiplexed Function select is done via PLLCR register. I2C Serial Data The SDA/QSPI_DIN and SDA2/GPIO55 bidirectional signals are the data input/output for the first and second serial I2C interface. Signals are multiplexed Function select is done via PLLCR register.
8.9
Serial Module Signals
The following signals transfer serial data between the two UART modules and external peripherals. All serial module signals can be used as gpi or gpo. The GPIO-FUNCTION and GPIO1-FUNCTION registers must be programmed to determine pin functions of the inputs and outputs. If used as gpo or gpi, UART functionality is lost.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 19
Signal Descriptions
Table 7. Serial Module Signals
Serial Module Signal Receive Data Description The RXD1_GPI27 and RXD2/ADIN2/GPI28 are the inputs on which serial data is received by the DUART. Data is sampled on RxD[1:0] on the rising edge of the serial clock source, with the least significant bit received first. The DUART transmits serial data on the TXD1/GPO27 and TXD2/GPO28 output signals. Data is transmitted on the falling edge of the serial clock source, with the least significant bit transmitted (LSB) first. When no data is being transmitted or the transmitter is disabled, these two signals are held high. TxD[1:0] are also held high in local loopback mode. The RTS1/GPO30 and RTS2/GPO31 request-to-send outputs indicate to the peripheral device that the DUART is ready to send data and requires a clear-to-send signal to initiate transfer. Peripherals drive the CTS1/GPI30 and CTS2/ADIN3/GPI31 inputs to indicate to the SCF5249 serial module that it can begin data transmission.
Transmit Data
Request To Send
Clear To Send
8.10 Timer Module Signals
The following signals are external interface to the two general-purpose SCF5249 timers. These 16-bit timers can capture timer values, trigger external events, or internal interrupts, or count external events. These pins can be reused as GPO or GPI. Registers GPIO-FUNCTION and GPIO1-FUNCTION must be programmed for this.
Table 8. Timer Module Signals
Serial Module Signal Timer Input Description Users can program the TIN0/GPI33 and TIN1/GPIO23 inputs as clocks that cause events in the counter and prescalars. They can also cause capture on the rising edge, falling edge, or both edges. The TOUT0/GPO33 and TOUT1/ADOUT/GPO35 programmable outputs pulse or toggle on various timer events.
Timer Output
8.11 Serial Audio Interface Signals
All serial audio interface signals can be programmed to serve as general purpose I/Os or as serial audio interface signals. The function is programmed using GPIO-FUNCTION and GPIO1-FUNCTION registers. NOTE The LRCK3 and SCLK3 signals are only used in the 160 MAPBGA package..
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 20 Freescale Semiconductor
Signal Descriptions
Table 9. Serial Audio Interface Signals
Serial Module Signal Serial Audio Bit Clock Description The SCLK1, SCLK2/GPIO48 and SCLK3/GPIO49, and SCLK4/GPIO50 multiplexed pins can serve as general purpose I/Os or serial audio bit clocks. As bit clocks, these bidirectional pins can be programmed as outputs to drive their associated serial audio (IIS) bit clocks. Alternately, these pins can be programmed as inputs when the serial audio bit clocks are driven internally. The functionality is programmed within the Audio module. During reset, these pins are configured as input serial audio bit clocks. The LRCK1, LRCK2/GPIO44, LRCK3/GPIO45, and LRCK/GPIO46 multiplexed pins can serve as general purpose I/Os or serial audio word clocks. As word clocks, the bidirectional pins can be programmed as inputs to drive their associated serial audio word clock. Alternately, these pins can be programmed as outputs when the serial audio word clocks are derived internally. The functionality is programmed within the Audio module. During reset, these pins are configured as input serial audio word clocks. The SDATAI1, SDATAI3/GPIO41, and SDATAI4/GPI42 multiplexed pins can serve as general purpose I/Os or serial audio inputs. As serial audio inputs the data is sent to interfaces 1and 3 respectively. The functionality of these pins is programmed with the GPIO-FUNCTION and GPIO1-FUNCTION registers. During reset, the pins are configured as serial data inputs. The SDATAO1/GPIO25 AND SDATAO2/GPI41 multiplexed pins can serve as general purpose I/Os or serial audio outputs. The functionality of these pins is programmed with registers GPIO-FUNCTION and GPIO1-FUNCTION. During reset, the pins are configured as serial data outputs.. The EF/GPIO19 multiplexed pin can serve as general purpose I/Os or error flag input. As error flag input, this pin will input the error flag delivered by the CD-DSP. EF/GPIO19 is only relevant for serial interface interface 1. The CFLG/GPIO18 multiplexed pin can serve as general purpose I/O or CFLG input. As CFLG input, the pin will input the CFLG flag delivered by the CD-DSP. CFLG/GPIO18 is only relevant for serial interface 1.
Serial Audio Word Clock
Serial Audio Data In
Serial Audio Data Out
Serial audio error flag
Serial audio CFLG
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 21
Signal Descriptions
8.12 Digital Audio Interface Signals
Table 10. Digital Audio Interface Signals
Serial Module Signal Digital Audio In Description The EBUIN1/GPI36, EBUIN2/GPI37, EBUIN3/ADIN0/GPI38, and EBUIN4/ADIN1/GPI39 multiplexed signals can serve as general purpose input or can be driven by various digital audio (IEC958) input sources. Both functionalities are always active. Input chosen for IEC958 receiver is programmed within the audio module. Input value on the 4 pins can always be read from the appropriate gpio register.. The EBUOUT1_GPO36 and EBUOUT2_GPO37 multiplexed pins can serve as general purpose I/O or as digital audio (IEC958) output. EBUOUT1 is digital audio out for consumer mode, EBUOUT2 is digital audio out for professional mode. The functionality of the pins is programmed with the GPIO-FUNCTION and GPIO1-FUNCTION register. During reset, the pin is configured as a digital audio output.
Digital Audio Out
NOTE The EBUOUT2 signal is only used on the 160 MAPBGA package.
8.13 Subcode Interface
There is a 3-line subcode interface on the SCF5249. This 3-line subcode interface allows the device to format and transmit subcode in EIAJ format to a CD channel encoder device. The three signals are described in Table 11.
Table 11. Subcode Interface Signal
Signal name RCK/GPIO51 SFSY/GPIO52 Description Subcode clock input. When pin is used as subcode clock, this pin is driven by the CD channel encoder. Subcode sync output This signal is driven high if a subcode sync needs to be inserted in the EFM stream. Subcode data output This signal is a subcode data out pin.
SUBR/GPIO53
NOTE The SUBR, SFSY, and the RCK signals are only used in the 160 MAPBGA package.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 22 Freescale Semiconductor
Signal Descriptions
8.14 Analog to Digital Converter (ADC)
The single output on the TOUT1/ADOUT/GPO35 pin provides the reference voltage in PDM format therefore this output requires an external integrator circuit (resistor/capacitor) to convert it to a DC level to be used by the external comparator circuit. Four external comparators compare the DC level obtained after filtering TOUT1/ADOUT/GPO35 with the relevant input signals. The outputs of the comparators are fed to the 4 ADIN inputs on the SCF5249: EBUIN3/ADIN0/GPI38, EBUIN4/ADIN1/GPI39, RXD2/ADIN2/GPI38 and CTS2/ADIN3/GPI31. Selection of function for pin TOUT1/ADOUT/GPO35 is done by writing GPIO function select register (determines if function is GPIO or not), and differentiation between timer and adout functions is done in the ADCONFIG Register.
8.15 Secure Digital/ MemoryStick Card Interface
The device has a versatile flash card interface that supports both SecureDigital and MemoryStick cards. The interface can either support one SecureDigital or two MemoryStick cards. No mixing of card types is possible. Table 12 gives the pin descriptions.
Table 12. Flash Memory Card Signals
Flash Memory Signal SCLKOUT/GPIO15 CMD_SDIO2/GPIO34 SDATA0_SDIO1/GPIO54 SDATA1_BS1/GPIO9 RSTO/SDATA2_BS2 Description Clock out for both MemoryStick interfaces and for SecureDigital Secure Digital command line MemoryStick interface 2 data i/o SecureDigital serial data bit 0 MemoryStick interface 1 data i/o SecureDigital serial data bit 1 MemoryStick interface 1 strobe SecureDigital serial data bit 2 MemoryStick interface 2 strobe Reset output signal Selection between Reset function and SDATA2_BS2 is done by programming PLLCR register. SecureDigital serial data bit 3
SDATA3/GPIO57
NOTE The SDATA0_SDIO1 and RSTO/SDATA2_BS2 signals are only used in the 160 MAPBGA package.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 23
Signal Descriptions
8.16 Queued Serial Peripheral Interface (QSPI)
Table 13. Queued Serial Peripheral Interface (QSPI) Signals
Serial Module Signal SCL_QSPICLK SDA_QSPIDIN QSPIDOUT_GPIO26 QSPICS0_GPIO29 QSPICS1_GPIO24 QSPICS2_GPIO21 QSPICS3_GPIO22 Description Multiplexed signal IIC interface clock or QSPI clock output Function select is done via PLLCR register. Multiplexed signal IIC interface data or QSPI data input. Function select is done via PLLCR register. QSPI data output 4 different QSPI chip selects
NOTE The QSPI interface is a high-speed serial interface allowing transmit and receive of serial data.
8.17 Crystal Trim
The XTRIM_GPIO38 output produces a pulse-density modulated phase/frequency difference signal to be used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will lock the crystal to the incoming digital audio signal.
8.18 Clock Out
The MCLK1/GPO39 and /MCLK2/GPO42 can serve as general purpose I/Os or as DAC clock outputs. When programmed as DAC clock outputs, these signals are directly derived from the crystal.
8.19 Debug and Test Signals
These signals interface with external I/O to provide processor status signals.
8.19.1 Test Mode
The TEST[3:0] inputs are used for various manufacturing and debug tests. For normal mode these inputs should be always be tied low. Use TEST0 to switch between background debug mode and JTAG mode. Drive TEST0 high for debug mode.
8.19.2 High Impedance
The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is independent of the clock.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 24 Freescale Semiconductor
Signal Descriptions
NOTE JTAG operation will override the HI_Z pin.
8.19.3 Processor Clock Output
The internal PLL generates this PSTCLK/GPO63 and output signal, and is the processor clock output that is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The PSTCLK/GPO63 is at the same frequency as the core processor and cache memory. The frequency will be twice the bus clock (SCLK) frequency.
8.19.4 Debug Data
The debug data pins, DDATA0_GPIO0, DDATA1_GPIO1, DDATA2_GPIO2, and DDATA3_GPIO4, are four bits wide. This nibble-wide bus displays captured processor data and break-point status.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 25
Signal Descriptions
8.19.5 Processor Status
The processor status pins, PST0_GPIO59, PST1_GPIO60, PST2_GPIO61, and PST3_GPIO62, indicate the SCF5249 processor status. During debug mode, the timing is synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer. .
Table 14. Processor Status Signal Encodings
PST[3:0] Definition (HEX) $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
Notes: 4. 5. Rev. B enhancement. These encodings are asserted for multiple cycles.
(BINARY) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Continue execution Begin execution of an instruction Reserved Entry into user-mode Begin execution of PULSE and WDDATA instructions Begin execution of taken branch or Synch_PC1 Reserved Begin execution of RTE instruction Begin 1-byte data transfer on DDATA Begin 2-byte data transfer on DDATA Begin 3-byte data transfer on DDATA Begin 4-byte data transfer on DDATA Exception processing2 Emulator mode entry exception processing2 Processor is stopped, waiting for interrupt2 Processor is halted2
8.20 BDM/JTAG Signals
The SCF5249 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed with background debug pins.
8.20.1 Test Clock
TCK is the dedicated JTAG test logic clock that is independent of the SCF5249 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. The internal JTAG controller logic is designed such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to lose state information. If TCK will not be used, it should be tied to ground.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 26 Freescale Semiconductor
Signal Descriptions
8.20.2 Test Reset/Development Serial Clock
The TEST[3:0] signals determine the function of the TRST/DSCLK dual-purpose pin. If TEST[3:0]=0001, the DSCLK function is selected. If TEST[3:0]= 0000, the TRST function is selected. TEST[3:0] should not be changed while RSTI = 1. When used as TRST, this pin will asynchronously reset the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose the ibypassi command. When this occurs, all the JTAG logic is benign and will not interfere with the normal functionality of the SCF5249 processor. Although this signal is asynchronous, Freescale recommends that TRST make only a 0 to 1 (asserted to negated) transition while TMS is held at a logic 1 value. TRST has an internal pullup so that if it is not driven low its value will default to a logic level of 1. However, if TRST will not be used, it can either be tied to ground or, if TCK is clocked, it can be tied to VDD. If it is tied to ground, it will place the JTAG controller in the test logic reset state immediately. If it is tied to VDD, it will cause the JTAG controller (if TMS is a logic 1) to eventually end up in the test logic reset state after 5 clocks of TCK. This pin is also used as the development serial clock (DSCLK) for the serial interface to the Debug Module.The maximum frequency for the DSCLK signal is 1/5 the BCLKO frequency.
8.20.3 Test Mode Select/Break Point
The TEST[3:0] signals determine the TMS/BKPT pin function. If TEST[3:0] =0001, the BKPT function is selected. If TEST[3:0] = 0000, then the TMS function is selected. TEST[3:0] should not change while RSTI = 1. When used as TMS, this input signal provides the JTAG controller with information to determine which test operation mode should be performed. The value of TMS and current state of the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state. This directly controls whether JTAG data or instruction operations occur. TMS has an internal pullup so that if it is not driven low, its value will default to a logic level of 1. However, if TMS will not be used, it should be tied to VDD. This pin also signals a hardware breakpoint to the processor when in the debug mode.
8.20.4 Test Data Input/Development Serial Input
The TDI/DS is a dual-function pin. If TEST[3:0] = 0001, then DSI is selected. If TEST[3:0] = 0000, then TDI is selected. When used as TDI, this input signal provides the serial data port for loading the various JTAG shift registers composed of the boundary scan register, the bypass register, and the instruction register. Shifting in of data depends on the state of the JTAG controller state machine and the instruction currently in the instruction register. This data shift occurs on the rising edge of TCK. TDI also has an internal pullup so that if it is not driven low its value will default to a logic level of 1. However, if TDI will not be used, it should be tied to VDD. This pin also provides the single-bit communication for the debug module commands.
8.20.5 Test Data Output/Development Serial Output
The TDO/DSO is a dual-function pin. When TEST[3:0] = 0001, then DSO is selected. When TEST[3:0] = 0000, TDO is selected. When used as TDO, this output signal provides the serial data port for outputting
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 27
Electrical Characteristics
data from the JTAG logic. Shifting out of data depends on the state of the JTAG controller state machine and the instruction currently in the instruction register. This data shift occurs on the falling edge of TCK. When TDO is not outputting test data, it is three-stated. TDO can also be placed in three-state mode to allow bussed or parallel connections to other devices having JTAG. This signal also provides single-bit communication for the debug module responses.
8.21 Clock and Reset Signals
These signals configure the SCF5249 and provide interface signals to the external system.
8.21.1 Reset In
Asserting RSTI causes the SCF5249 to enter reset exception processing. When RSTI is recognized, the data bus is tri-stated.
8.21.2 System Bus Input
The CRIN signal is the system clock input. The device has no on-chip clock oscillator, and needs an external oscillator.
9
Electrical Characteristics
Table 15. Maximum Ratings
Rating Supply Core Voltage Maximum Core Operating Voltage Minimum Core Operating Voltage Supply I/O Voltage Maximum I/O Operating Voltage Minimum I/O Operating Voltage Input Voltage Storage Temperature Range Symbol Vcc Vcc Vcc Vcc Vcc Vcc Vin Tstg Value -0.5 to +2.5 +1.98 +1.62 -0.5 to +4.6 +3.6 +3.0 -0.5 to +6.0 -65 to150 Units V V V V V V V
o
C
Table 16. Operating Temperature
Characteristic Maximum Operating Ambient Temperature Minimum Operating Ambient Temperature
Note:
Symbol TAmax TAmin
Value 851 0
Units
C oC
This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature does not exceed 105C.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 28 Freescale Semiconductor
Electrical Characteristics
Table 17. DC Electrical Specifications (Vcc = 3.3 Vdc + 0.3 Vdc)
Characteristic Operation Voltage Range for I/O Input High Voltage Input Low Voltage Input Leakage Current @ 0.0 V /3.3 V During Normal Operation Hi-Impedance (Three-State) Leakage Current @ 0.0 V/3.3 V During Normal Operation Output High Voltage IOH = 8mA1, 4mA2, 2mA3 Output Low Voltage IOL = 8mA1, 4mA2, 2mA3 Schmitt Trigger Low to High Threshold Point6 Schmitt Trigger High to Low Threshold Point6 Load Capacitance (DATA[31:16], DCL0, DCL1, SCLK[4:1], SCLKOUT, EBUOUT[2:1], LRCK[4:1], SDATAO[2:1], CFLG, EF, DBCDDATA[3:0], DBCPST[3:0], CNPSTCLK, IDEDIOR, IDEDIOW, IORDY, SRE, SWE) Load Capacitance (ADDR[25, 23:9], SCLK) Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM, SDRAMCS[2:1],, SDUDQM, SDWE, BUFENB[2:1]) Load Capacitance (SDA, SDA2, SCL, SCL2, CMDSDIO2, SDATA2BS2, SDATA1BS1, SDATA0SDIO1, CS[1:0], OE, R/W, TA, TXD[2:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT[1:0], QSPIDOUT, QSPICS[3:0], GP[6:5]) Capacitance5, Vin = 0 V, f = 1 MHz Symbol Vcc VIH VIL Iin ITSI VOH VOL VT+ VTCL Min 3.0 2 -0.3 2.4 1.47 Max 3.6 5.5 0.8 1 1 0.4 .95 50 Units V V V A A V V V V pF
CL CL CL
-
40 30 20
pF pF pF
CIN
-
6
pF
1. DATA[31:16], ADDR[25, 23:9], PSTCLK, SCLK 2. SCL, SDA, PST[3:0], DDATA[3:0], TDSO, SDRAS, SDCAS, SDWE, SDRAMCS[2:1], SDLDQM, SDUDQM, R/W 3. TOUT[1:0], RTS[2:0], TXD[2:1], SCLK[4:1] 4. BKPT/TMS, DSI/TDI, DSCLK/TRST 5. Capacitance CIN is periodically sampled rather than 100% tested. 6. SCLK[4:1], SCL, SCL2, SDA, SDA2, CRIN, RSTI
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 29
Electrical Characteristics
9.1
Supply Voltage Sequencing and Separation Cautions
Figure 2 shows two situations to avoid in sequencing the CoreVdd and PADVdd (I/O) and PLLL supplies.
Figure 2. Supply Voltage Sequencing and Separation Cautions
CoreVdd supply should not be allowed to rise early (1). This is usually avoided by running the regulator for the CoreVdd supply (1.8 V) from the voltage generated by the 3.3V supply (PADVdd). This keeps the CoreVdd supply from rising faster than PADVdd supply. Also CoreVdd, PLLGVdd, PLLCVdd supply should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies. The series diodes forward bias when the difference between PADVdd and CoreVdd reaches approximately 2.1V, causing CoreVdd to rise as PADVdd ramps up. When the CoreVdd regulator begins proper operation, the difference between supplies should not exceed 1.5 V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: PADVdd, >= CoreVdd, PLLGVdd, >= (PADVdd - 2.1 V). The PLL core supplies (PLLGVdd and PLLCVdd) should comply with these constraints just as the CoreVdd does. In practice, PLLGVdd and PLLCVdd are typically connected directly to the CoreVdd with some filtering. Further, the PLL PAD supply (PLL1VDD) would be connected directly to the PAD supply via some filtering.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 30 Freescale Semiconductor
Electrical Characteristics
Figure 3. Example Circuit to Control Supply Sequencing
When a DC-DC convertor is used in the system to generate the 1.8V supply, additional care is required. If possible, the 1.8V DC-DC convertor should be supplied by the 3.3V supply. If this is impossible or considered inefficient, the designer needs to ensure that the rise time of the 1.8V supply still complies with the recommendations stated above. Adding the 3 diodes will help resolve issues associated with a slow rise time of the 1.8V supply. Further, a Schotty diode could be added between the supplies, which would have the effect of holding the 1.8V supply to match the 3.3V supply should the 1.8V supply come-up first. This diode also has the function of ensuring that there is not a large voltage differential between the Core supply and the PAD supply during power-down. Refer to the M5249C3 Reference Board Useris Manual for the recommended diode types. A further note is the recommendation for hard resetting of the device. Freescale recommends using a dynamic reset circuit. This allows for control of the voltage at which the reset will be released and ensure that the correct voltage level at the RESET pin is achieved in all cases. Passive (RC) reset networks do not always achieve the desired results.
Figure 4. SCF5249 Power Supply
NOTE The following signals are not available on the 144 QFP package.
Table 18. 160 MAPBGA Ball Assignments
160MAPBGA Ball Number E3 G4 H3 K3 Function CMD_SDIO2 SDATA0-SDIO1 RSTO/SDATA2_BS2 A25 GPO8 GPIO GPIO34 GPIO54
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 31
Electrical Characteristics
Table 18. 160 MAPBGA Ball Assignments (continued)
160MAPBGA Ball Number L4 L8 N8 P9 K11 G12 F13 F12 E8 B8 E7 A7 Function QSPI_CS1 QSPI_CS3 SDRAM_CS2 EBUOUT2 BUFENB2 SUBR SFSY RCK SRE LRCK3 SWE SCLK3 GPIO GPIO24 GPIO22 GPIO7 GPO37 GPIO17 GPIO53 GPIO52 GPIO51 GPIO11 GPIO45 GPIO12 GPIO49
Table 19. Clock Timing Specification
NUM Characteristic Min CRIN Frequency1 C5 C6 C7 C8
Note:
Units Max 33.86 -- 60 -- 55 MHz nSec % nSec %
11.29 7.1 40 14.2 45
PSTCLK cycle time PSTCLK duty cycle BCLK cycle time BCLK duty cycle
There are only three choices for the valid Audio frequencies 11.29 MHz, 16.93 MHz, or 33.86 MHz; no other values are allowed. The System Clock is derived from one of these crystals via an internal PLL.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 32 Freescale Semiconductor
Electrical Characteristics
CRIN
PSTCLK
C6 C6 C7
BCLK
C8 C8
Figure 5. Clock Timing Definition
NOTE Signals above are shown in relation to the clock. No relationship between signals is implied or intended.
9.1.1
Processor Bus Input Timing Specification
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the SCLK output. All other timing relationships can be derived from these values.
Table 20. External Bus Input Timing Specifications
Num Characteristica Symbol B0 B1 B2 B4 SCLK Control input valid to SCLK highb SCLK high to control inputs validb Data input (D[31:0]) valid to SCLK high tCYC tCVCH tCHCII tDIVCH Min 14.26 10 2 6 Max -- -- -- -- ns ns ns ns Units
Table 20 lists processor bus input timings.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 33
Electrical Characteristics
Table 20. External Bus Input Timing Specifications (continued)
Num Characteristica Symbol B5 SCLK high to data input (D[31:0]) invalid tCHDII Min 2 Max -- ns Units
a. Timing specifications have been indicated taking into account the full drive strength for the pads. b. TA pin is being referred to as control input.
9.1.2
Processor Bus Output Timing Specifications
Table 21 lists processor bus output timings.
Table 21. External Bus Output Timing Specifications
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 34 Freescale Semiconductor
Electrical Characteristics
Figure 6. Read/Write (Internally Terminated) Timing
Figure 7. Read Bus Cycle Terminated by TA
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 35
Electrical Characteristics
Table 22. SDRAM Timing
Figure 8. SDRAM Read Cycle
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 36 Freescale Semiconductor
Electrical Characteristics
Figure 9. SDRAM Write Cycle Table 23. Debug AC Timing Specification
Num Characteristic Min D1 D2 D31 D4
1. 2.
Units Max 6 -- -- -- nSec nSec nSec nSec
PSTCLK to signal Valid (Output valid) PSTCLK to signal Invalid (Output hold) Signal Valid to PSTCLK (Input setup) PSTCLK to signal Invalid (Input hold)
--1.8 3 5
DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is required. AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 37
Electrical Characteristics
PSTCLK D3
D4
DSCLK D3 D1
D4
DSI PST[3:0] DDATA[3:0] DSO
D2
Figure 10. Debug Timing Definition Table 24. Timer Module AC Timing Specification
Num Characteristic Min T1 T2 T3 T4 T5 T6 T7 TIN Cycle time TIN Valid to BCLK (input setup) SCLK to TIN Invalid (input hold) SCLK to TOUT Valid (output valid) SCLK to TOUT Invalid (output hold) TIN Pulse Width TOUT Pulse Width tbd tbd tbd -- tbd tbd tbd Max -- -- -- tbd -- -- -- bus clocks nSec nSec nSec nSec bus clocks bus clocks Units
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 38 Freescale Semiconductor
Electrical Characteristics
SCLK
T6
TIN
T2
T3
TIN
T1 T7
TOUT
T4
T5
Figure 11. Timer Module Timing Definition Table 25. UART Module AC Timing Specifications
Num Characteristic Min U1 U2 U3 U4 U5 U6 U7 U8 RXD Valid to BCLK (input setup) SCLK to RXD Invalid (input hold) CTS Valid to SCLK (input setup) SCLK to CTS Invalid (input hold) SCLK to TXD Valid (output valid) SCLK to TXD Invalid (output hold) SCLK to RTS Valid (output valid) SCLK to RTS Invalid (output hold) tbd tbd tbd tbd --tbd --tbd Max -- -- -- -- tbd -- tbd -- nSec nSec nSec nSec nSec nSec nSec nSec Units
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 39
Electrical Characteristics
SCLK U1 RXD U2 U3 CTS U4 U5 TXD U6 U7 RTS U8
Figure 12. UART Timing Definition Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA
Num M1 M2 M3 M4 M5 M6 M7 M8 Characteristic Min Start Condition Hold Time Clock Low Period SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V) Data Hold Time SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V) Clock High time Data Setup Time Start Condition Setup Time (for repeated start condition only) tbd tbd -- tbd -- tbd tbd tbd Max -- -- tbd -- tbd -- -- -- bus clocks bus clocks mSec nSec mSec bus clocks nSec bus clocks Units
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 40 Freescale Semiconductor
Electrical Characteristics
Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA
Num M9 Characteristic Min Stop Condition Setup Time tbd Max -- bus clocks Units
Table 27. I2C-Bus Output Timing Specifications Between SCL and SDA
Num M11 M21 M32 M41 M5
3
Characteristic Min Start Condition Hold Time Clock Low Period SCL/SDA Rise Time (VIL= 0.5 V to VIH = 2.4 V) Data Hold Time SCL/SDA Fall Time (VIH= 2.4 V to VIL = 0.5 V) Clock High time Data Setup Time Start Condition Setup Time (for repeated start condition only) Stop Condition Setup Time tbd tbd -- tbd -- tbd tbd tbd tbd Max -- -- tbd -- tbd -- -- -- --
Units
bus clocks bus clocks mSec bus clocks nSec bus clocks bus clocks bus clocks bus clocks
M61 M71 M81 M91
1.
Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the MFDR; however, numbers given in the above table are the minimum values. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. Specified at a nominal 20 pF load.
2.
3.
M2 SCL M1 M4
M6 M7 M8
M5 M3 M9
SDA
Figure 13. I2C Timing Definition
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 41
Electrical Characteristics
Table 28. I2C Output Bus Timings
Num M103 M11 M121 M132
1.
Characteristic Min SCL, SDA Valid to SCLK (input setup) SCLK to SCL, SDA Invalid (input hold) SCLK to SCL, SDA Low (output valid) SCLK to SCL, SDA Invalid (output hold) tbd tbd -- tbd Max -- -- tbd --
Units
nSec nSec nSec nSec
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL or SDA are actively being driven or held low by the processor. SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular clock is required.
2. 3.
SCLK
M10
SCL, SDA IN
M11
SCL, SDA OUT
M12
SCL, SDA OUT M13 Figure 14. I2C and System Clock Timing Relationship
Table 29. General-Purpose I/O Port AC Timing Specifications
Num Characteristic Min P1 P2 GPIO Valid to SCLK (input setup) SCLK to GPIO Invalid (input hold) tbd tbd Max -- -- nSec nSec Units
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 42 Freescale Semiconductor
Electrical Characteristics
Table 29. General-Purpose I/O Port AC Timing Specifications
Num Characteristic Min P3 P4 SCLK to GPIO Valid (output valid) SCLK to GPIO Invalid (output hold) -- tbd Max tbd -- nSec nSec Units
SCLK P1
GPIO IN P2 P3 GPIO OUT P4
Figure 15. General-Purpose Parallel Port Timing Definition Table 30. IEEE 1149.1 (JTAG) AC Timing Specifications
Num Characteristic Min J1 J2a J2b J3a J3b J4 J5 J6 J7 TCK Frequency of Operation TCK Cycle Time TCK Clock Pulse High Width TCK Clock Pulse Low Width TCK Fall Time (VIH=2.4 V to VIL=0.5 V) TCK Rise Time (VIL=0.5 v to VIH=2.4 V) TDI, TMS to TCK rising (Input Setup) TCK rising to TDI, TMS Invalid (Hold) Boundary Scan Data Valid to TCK (Setup) TCK to Boundary Scan Data Invalid to rising edge (Hold) 0 100 25 25 -- -- 8 10 tbd tbd Max 10 5 5 -- -- -- -- MHz nSec nSec nSec nSec nSec nSec nSec nSec nSec Units
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 43
Electrical Characteristics
Table 30. IEEE 1149.1 (JTAG) AC Timing Specifications
Num Characteristic Min J8 J9 J10 J11 J12 TRST Pulse Width (asynchronous to clock edges) TCK falling to TDO Valid (signal from driven or three-state) TCK falling to TDO High Impedance TCK falling to Boundary Scan Data Valid (signal from driven or three-state) TCK falling to Boundary Scan Data High Impedance 12 -- -- -- -- Max -- 15 15 tbd tbd nSec nSec nSec nSec nSec Units
J1 J2A J4 J2B
J3A J3B
TCK
TDI, TMS J5 BOUNDARY SCAN DATA INPUT J6 J7
TRST J8 J9 TDO J10 BOUNDARY SCAN DATA OUTPUT J11 J12
Figure 16. JTAG Timing
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 44 Freescale Semiconductor
Electrical Characteristics
9.2
JTAG Timing Definition IIS Module AC Timing Specifications
Table 31. SCLK INPUT, SDATAO OUTPUT Timing Specifications
Name TU TD Characteristic Min SCLK fall to SDATAO rise SCLK fall to SDATAO fall ----Max 25 25 ns ns Unit
SCLK
(INPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 17. SCLK Input, SDATA Output Timing
Table 32. SCLK OUTPUT, SDATA0 OUTPUT Timing Specifications
Name TU TD Characteristic Min SCLK fall to SDATAO rise SCLK fall to SDATAO fall ----Max 3 3 ns ns Unit
SCLK
(OUTPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 18. SCLK Output, SDATAO Output Timing Diagram
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 45
Pin-Out and Package Information
Table 33. SCLK INPUT, SDATAI INPUT Timing Specifications
Name TSU TH Characteristic Min SDATAI IN to SCLKn SCLK rise to SDATAI -5 3 Max -- -- ns ns Unit
SCLK (INPUT OR OUTPUT)
SDATA1, 3, 4 (INPUT)
TSU
TH
Figure 19. SCLK Input/Output, SDATAI Input Timing Diagram
10
Pin-Out and Package Information
10.1 Pinning Chart
Table 34. 144 QFP Pin Assignments
144 QFP Pin Number 01
Name
Type
Description
SCL/QSPI_CLK
I/O
IIC clock/QSPI clock pin function select is PLLCR(11) static chip select 0 SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr sdram clock output
02 03 04 05 06 07 08 09
CS0 A21 A11 A10 A9 A18 A17 BCLK/GPIO10
O O O O O O O I/O
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 46 Freescale Semiconductor
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 10 11 12
Name
Type
Description
SCLK_OUT/GPIO15 BCLKE SDA/QSPI_DIN
I/O O I/O
MemoryStick/SD sdram clock enable output IIC data/QSPI data in function select is PLLCR(11) data SDRAM address / static adr SDRAM UDQM error flag input data data data PAD-GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
DATA24 A22 SDUDQM EF/GPIO19 DATA25 DATA26 DATA27 PAD-GND DATA28 DATA29 SDATA3/GPIO56 DATA30 BUFENB1/GPIO57 DATA31 CORE-VDD A13 CORE-GND A23 A14 A15 A16 PAD-VDD A19
I/O O O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O
data data SD interface data line data external buffer 1 enable data CORE-VDD
O
SDRAM address / static adr CORE-GND
O O O O
SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr SDRAM address / static adr PAD-VDD
O
SDRAM address / static adr
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 47
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
Name
Type
Description
A20 TEST2 SDRAM-CS1 SDATA1_BS1/GPIO9 SDRAS SDCAS SDWE SDLDQM GPIO5 QSPI_CS0/GPIO29 QSPI_DOUT/GPIO26 GPIO6 DATA21 DATA19 QSPI_CS2/GPIO21 DATA20 DATA22 DATA18 DATA23 DATA17 PADD-VDD DATA16 CFLG/GPIO18 EBUOUT1/GPO36 CORE-GND EBUIN3/ADIN0/GPI38
O I O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
SDRAM address / static adr test SDRAM chip select out 1 Memory Stick / SD SDRAM RAS SDRAM CAS SDRAM write enable SDRAM LDQM GPIO5 QSPI chip select 0 QSPI data out GPIO6 data data QSPI chip select 2 data data data data data PAD-VDD
I/O I/O O
data CFLG input audio interfaces EBU out 1 CORE-GND
I
audio interfaces EBU in 3 / AD convertor input0
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 48 Freescale Semiconductor
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Name
Type
Description
EBUIN2/GPI37 CORE-VDD SCL2/GPIO3 RSTI TOUT1/ADOUT/GPO35 LRCK2/GPIO44 OE SDA2/GPIO55 SDATAO2/GPO41 SCLK2/GPIO48 PAD-GND TEST3 SDATAO1/GPIO25 LRCK1 LRCK4/GPIO46 SDATAI4/GPI42 SCLK1 SCLK4/GPIO50 TA/GPIO20 SDATAI1 EBUIN1/GPI36 PLLGRDVDD PLLGRDGND PLLPADGND PLLPADVDD PLLCOREGND PLLCOREVDD
I
audio interfaces EBU in 2 CORE-VDD
I/O I O O O I/O O I/O
IIS2 clock line Reset timer output 1 / AD output audio interfaces EBU out 1 Output Enable IIS2 data audio interfaces serial data output 2 audio interfaces serial clock 2 PAD-GND
I I/O I/O I/O I I/O I/O I/O I I
test audio interfaces serial data output 1 audio interfaces word clock 1 audio interfaces word clock 4 audio interfaces serial data in 4 audio interfaces serial clock 1 audio interfaces serial clock 4 Transfer acknowledge audio interfaces serial data in 1 audio interfaces EBU in 1 PLLGRDVDD PLLGRDGND PLLPADGND PLLPADVDD PLLCOREGND PLLCOREVDD
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 49
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
Name
Type
Description
IDE-DIOW/GPIO14 CRIN IDE-DIOR/GPIO13 IDE-IORDY/GPIO16 MCLK1/GPO39 MCLK2/GPO42 XTRIM/GPO38 TRST/DSCLK CORE-VDD RW_B TMS/BKPT CORE-GND TCK PAD-GND PST3/GPIO62 CNPSTCLK/GPO63 PST1/GPIO60 PAD-VDD PST2/GPIO61 PST0/GPIO59 TDI/DSI TEST0 TIN0/GPI33 HI-Z DDATA3/GPIO4 TOUT0/GPO33 DDATA1/GPIO1
I/O I I/O I/O O O O I
ide diow crystal ide dior ide iordy Audio master clock output 1 Audio master clock output 2 audio interfaces X-tal trim Debug / interrupt monitor output 2 CORE-VDD
O I
Bus write enable JTAG/debug CORE-GND
I
JTAG PAD-GND
I/O O I/O
debug debug debug PAD-VDD
I/O I/O I I I I I/O O I/O
debug debug jtag/debug test timer input 0 jtag debug timer output 0 debug
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 50 Freescale Semiconductor
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 116 117
Name
Type
Description
DDATA2/GPIO2 CTS2_B/ADIN3/GPI31
I/O I
debug second UART clear / AD input 3 debug second UART receive data input / AD input 2 JTAG/debug second UART request to send audio interfaces serial data input 3 first UART clear to send second UART transmit data output first UART request to send audio interfaces EBU input 4 / AD input 1 first UART transmit data output first UART receive data input chip select 1 CORE-GND
118 119
DDATA0/GPIO0 RXD2/GPI28/ADIN2
I/O I
120 121 122 123 124 125 126
TDSO RTS2_B/GPO31 SDATAI3/GPI41 CTS1_B/GPI30 TXD2/GPO28 RTS1_B/GPO30 EBUIN4/ADIN1/GPI39
O O I I O O I
127 128 129 130 131 132 133 134 135 136 137 138 139 140
TXD1/GPO27 128 RXD1/GPI27 CS1/GPIO58 CORE-GND A1 TIN1/GPIO23 A2 A3 PAD-GND A4 A6 A5 A8 A7
O I I/O
O I/O O O
SDRAM address / static adr Timer input 1 address address PAD-GND
O O O O O
address address address address address
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 51
Pin-Out and Package Information
Table 34. 144 QFP Pin Assignments (continued)
144 QFP Pin Number 141 142 143 144
Name
Type
Description
CORE-VDD A12 TEST1 PAD-VDD O I
CORE-VDD address test PAD-VDD
10.2 Package
The SCF5249 is assembled in 144-pin QFP package. Thermal characteristics are not available at this time.
SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 52 Freescale Semiconductor
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SCF5249 Integrated ColdFire(R) Microprocessor Data Sheet, Rev. 3 Freescale Semiconductor 55
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